This invention relates to a printed wiring board forming a wiring pattern thereon and in particular relates to a printed wiring board able to be suitably used in a multilayer build-up wiring board and a manufacturing method of the printed wiring board.
A method for alternately building-up an insulating layer and a conductor layer in a core substrate is adopted at present to realize an increase in density of the multilayer printed wiring board. Here, there are two kinds of methods constructed by full additive and semi-additive methods as the built-up method. A manufacturing process of a conductor circuit onto an interlayer resin insulating layer of the multilayer printed wiring board using this semi-additive method will be explained next with reference to FIG. 32.
First, an insulating layer 250 having an opening 250a as a via hole is formed on each of both faces of a core substrate 230. An electroless plating copper film 252 is uniformly formed on a surface of the interlayer resin insulating layer 250 (FIG. 32(A)). An unillustrated resist film for forming a resist is adhered onto the electroless plating copper film 252. Thereafter, the resist film is exposed and developed and a resist 254 for plating is formed (FIG. 32(B)). Thereafter, an electrolytic plating copper film 256 is deposited in a nonforming portion of the resist 254 by dipping the core substrate 230 into an electrolytic plating liquid and flowing an electric current through the electroless plating copper film 252 (FIG. 32(C)). Wiring patterns 258a, 258b and a via hole 260 are then formed by separating the resist 254 and separating the electroless plating copper film 252 below the resist 254 by etching. Similar processes are repeated and an interlayer resin insulating layer 350, a wiring pattern 358 and a via hole 360 are further formed (FIG. 32(E)).
FIG. 33(B) shows a Bxe2x80x94B section of FIG. 32(E). At present a design of pulling-out wiring branched from one main wiring is adopted to prevent disconnection in the multilayer printed wiring board. Therefore, a crossing portion X formed in a T-character shape is formed as shown in FIGS. 33(A) and 33(B).
However, there is a case in which the wiring pattern is disconnected in the above crossing portion X. Namely, the wiring pattern 258 is formed in the nonforming portion of the resist 254 as mentioned above with reference to FIG. 32(C). However, as shown by the crossing portion X in FIG. 33(A), no plating liquid can be sufficiently moved around a corner portion C in which wall faces 258xcex2, 258xcex2 of the wiring pattern 258 in the crossing portion cross at an angle (here a right angle) equal to or smaller than 90xc2x0. Accordingly, the wiring pattern is made thin so that disconnection is caused in a particular case.
Further, as shown in FIG. 33(B), the wiring pattern 258b formed by a metal such as copper, etc. is suddenly curved in the crossing portion X. Therefore, a case in which stress is concentrated to the corner portion C of the crossing portion in repetition of thermal contraction and a crack CL is thereby caused in the wiring pattern and the wiring pattern is thus disconnected.
Furthermore, when the wiring pattern 258b is coated with the interlayer resin insulating layer 350 as mentioned above with reference to FIG. 32(E), there is a case whereby an air bubble B is left between the wiring pattern 258b and the interlayer resin insulating layer 350 in the corner portion C of the crossing portion as shown in FIG. 33(B). At this point, when the air bubble B is left in a lower layer of the interlayer resin insulating layer 350, the air bubble B is expanded in the thermal contraction of the printed wiring board and causes a breakdown of the printed wiring board.
In a further background art of the present invention, a multilayer build-up wiring board is formed by alternately laminating an interlayer resin insulating layer and a wiring layer on a core substrate. The multilayer build-up wiring board is mainly manufactured by an additive method at present. The above wiring layer is formed in an opening portion of a resist formed on the interlayer resin insulating layer by electrolysis or by electroless plating. Upper and lower wiring layers are electrically connected to each other by a via hole extending through the interlayer resin insulating layer. Each of these wiring layers is constructed by a via hole land used as a receiving pan of the via hole, a wiring pattern, a solid portion having a high potential applied by a power source, etc. and having a function similar to the function of a capacitor electrode, etc. Here, minimum values of a size of the via hole land, a width of the wiring pattern and an insulating distance between the via hole land and the wiring pattern are determined by resolution of the resist, an attaching degree of plating, etc. The via hole land and the wiring pattern are manufactured by setting the size, the width and the insulating distance to be greater than these minimum values respectively.
The multilayer build-up wiring board for a package functions as a connector for electrically connecting an electronic part such as an IC chip, etc. mounted to an upper face of the multilayer build-up wiring board to a printed wiring board such as a mother board, etc. located on a lower face of the multilayer build-up wiring board. Here, it is required that a line width of the wiring pattern, an insulating distance and a land diameter are reduced to cope with an increase in density of a connecting portion of the electronic part and the printed wiring board. However, when these values are set smaller than the above minimum values respectively, no desirable wiring can be formed by dispersion of a slight process condition in order that the probability of generation of disconnection of the wiring, a short-circuit of wirings, etc. is increased and yield is reduced.
In contrast to this, it is also possible to cope with the above increase in density by increasing the number of build-up layers of the multilayer build-up wiring board without reducing the line width of the wiring pattern and the insulating distance. However, if the number of build-up layers is increased, a manufacturing process becomes exponentially complicated and reliability and yield are reduced.
Here, in the further background art of the present invention, thick and thin portions of the wiring pattern are formed in the multilayer build-up wiring board of the prior art so that resistance is not uniform and has a inferior influence on propagation of an electric signal. Further, no thickness of an interlayer resin insulating layer (30 xcexcm) formed on an upper layer of the wiring pattern (having 15 xcexcm average in thickness) is uniformed so that no electric characteristics of the wiring board can be constantly set. Therefore, it is difficult to improve performance of the multilayer build-up wiring board.
When the inventors of this application investigated this cause, it was found that the thickness of the interlayer resin insulating layer was dispersed by an arranging density of the wiring pattern. For example, there is a case in which the thickness of the interlayer resin insulating layer is thin in a high wiring density portion and is thick in a low wiring density portion (having no signal line therearound). In contrast to this, there is also a case in which the thickness of the interlayer resin insulating layer is thick in a high wiring density portion and is thin in a low wiring density portion.
It is considered from these facts initially that the thickness of the interlayer resin insulating layer is dispersed by plating thickness. In particular, it is considered that the thickness of a signal line is increased in the low wiring density portion since an electric field is concentrated to this low wiring density portion in electrolytic plating. In contrast to this, it is considered that the thickness of the signal line is reduced in the high wiring density portion since the electric field is dispersed.
Furthermore, for a second reason it is considered that the thickness of the wiring pattern is dispersed by a moving-round of an etching liquid. The multilayer build-up wiring board at present is mainly formed by the semi-additive method to obtain higher performance. In the semi-additive method, after an electroless plating film is uniformly formed in the interlayer resin insulating layer, a resist pattern is formed and a conductor layer is formed by forming an electrolytic plating film in a nonforming portion of the resist by flowing an electric current through the electroless plating film. Here, after the electrolytic plating film is formed and the resist is separated, the electroless plating film below the resist is removed therefrom by light etching. However, in this light etching, no etching liquid can be sufficiently moved around the high wiring density portion so that the thickness of the wiring pattern can be increased. In contrast to this, the etching liquid is moved around the low wiring density portion excessively so that the thickness of the wiring pattern is reduced and a line width is also narrowed in a particular case.
In a further background art of the present invention, a conductor layer within a multilayer core substrate and a build-up wiring layer in a package substrate in the prior art are connected to each other by arranging an inner layer pad wired to a surface of the multilayer core substrate from a through hole and connecting a via hole to this inner layer pad. Namely, the inner layer pad for connecting the via hole to an upper layer is added to a land of the through hole, or the inner layer pad for connecting the via hole is connected to the land of the through hole through wiring.
However, in a land shape of the prior art, a through hole distance is widened to hold mutual insulation of the inner layer pad and the number of through holes formed in the multilayer core substrate is limited by this land shape.
In contrast to this, the number of bumps formed on a rear face of the package substrate is set to be greater than the number of bumps formed on a front side of the package substrate. This is because wirings from plural bumps on the rear face are connected to the bumps on the front side while these wirings on the rear face are integrated with each other. For example, power lines requiring low resistance to a signal line are set to 20 lines in the bumps on the rear face (on a mother board side), but are integrated as one line on the front face (an IC chip side).
Here, it is desirable to set the number of upper build-up wiring layers and the number of lower build-up wiring layers to be equal to each other, i.e., minimize the layer numbers that wirings can be integrated with each other at the same pace in build-up wiring layers formed on the front side of the core substrate and build-up wiring layers formed on the rear side of the core substrate. However, as mentioned above, the number of through holes able to be formed in the multilayer core substrate is limited. Therefore, in the package substrate of the prior art, wirings are integrated with each other to a certain extent in the build-up wiring layers on the rear side and are then connected to the build-up wiring layers on the front side through the through holes of the multilayer core substrate. Namely, since the wiring density is reduced in the build-up wiring layers on the front side, the same layer number as the number of build-up wiring layers on the rear side is not originally required. However, when the number of build-up wiring layers on the front and rear sides are set to be different to each other, a warp is caused by an asymmetric property. Therefore, the number of build-up wiring layers on the front and rear sides are set to be equal to each other. Namely, since the number of through holes formed in the multilayer core substrate is limited, the number of build-up wiring layers on the rear side must be increased and build-up wiring layers on the front side must be further formed to such a degree that the number of build-up wiring layers on the front side is equal to the increased number of build-up wiring layers on the rear side.
Namely, in the printed wiring board (package substrate) of the prior art, since the number of build-up layers is increased, problems exist whereby the connection reliability of upper and lower layers is reduced and the cost of the package substrate is increased and, thickness and weight of the package substrate is excessively increased.
To solve the above-mentioned problems, an object of the present invention is to provide a printed wiring board and a manufacturing method of the printed wiring board in which there is no disconnection caused in a wiring pattern.
An object of the present invention is to provide a printed wiring board of high density which is able to be manufactured with a high yield.
An object of the present invention is to provide a printed wiring board having superior uniform properties of thickness of a wiring pattern and an interlayer resin insulating layer.
An object of the present invention is to provide a printed wiring board which is able to reduce the number of build-up layers by increasing the density of through holes formed in a core substrate and to provide a manufacturing method of the printed wiring board.
To achieve the above objects, claim 1 resides in a printed wiring board having a wiring pattern on a substrate having an insulating substrate or an interlayer resin insulating layer, and technically characterized in that a filet is added to a crossing portion of said wiring pattern.
In the printed wiring board of claim 1, since the filet is added to the crossing portion of the wiring pattern of the printed wiring board, no wiring pattern is made thin and is disconnected in the crossing portion. Further, no crack is caused by thermal contraction.
Claim 2 resides in a printed wiring board having a wiring pattern on a substrate having an insulating substrate or an interlayer resin insulating layer, and technically characterized in that
a filet is added to a corner portion equal to or smaller than 90xc2x0 in a crossing portion of said wiring pattern.
In the printed wiring board of claim 2, since the filet is added to the corner portion equal to or smaller than 90xc2x0 in the crossing portion of the wiring pattern of the printed wiring board, no wiring pattern is made thin and is disconnected in the crossing portion. Further, no crack is caused by thermal contraction.
In the printed wiring board of claim 3, the filet is added to the crossing portion of the wiring pattern of the printed wiring board and no stress is concentrated to the crossing portion so that no wiring pattern is disconnected. Further, no air bubbles are left between the crossing portion of the wiring pattern and the interlayer resin insulating layer so that reliability of the printed wiring board is improved.
Claim 4 resides in a manufacturing method of a printed wiring board comprising:
a process for forming a resist having an opening portion for forming a wiring pattern on a substrate having an insulating substrate or an interlayer resin insulating layer; and
a process for forming the wiring pattern by depositing a metallic layer in the opening portion of the resist;
the manufacturing method being technically characterized in that
a corner portion equal to or smaller than 90xc2x0 in a crossing portion of the wiring pattern is chamfered in the process for forming said resist.
In the manufacturing method of the printed wiring board of claim 4, the corner portion equal to or smaller than 90xc2x0 in the crossing portion of the wiring pattern is chamfered in the process for forming the resist having the opening portion for forming the wiring pattern, and the resist is formed. The wiring pattern is formed such that this chamfering portion is set to a filet. Here, since the filet is added to the corner portion, no wiring pattern is made thin and is disconnected in the crossing portion.
Claim 5 resides in a manufacturing method of a printed wiring board technically characterized in that the manufacturing method comprises:
a process for forming a resist having an opening portion for forming a wiring pattern by chamfering a corner portion equal to or smaller than 90xc2x0 in a crossing portion of the wiring pattern in a process for forming the resist on a substrate having an insulating substrate or an interlayer resin insulating layer;
a process for forming the wiring pattern by depositing a metallic layer in the opening portion of the resist;
a process for forming the interlayer resin insulating layer in an upper layer of said wiring pattern; and
a process for forming the wiring pattern in an upper layer of said interlayer resin insulating layer.
In the printed wiring board of claim 5, the resist is formed by chamfering a portion constituting the corner portion equal to or smaller than 90xc2x0 in the crossing portion of the wiring pattern in the process for forming the resist having the opening portion for forming the wiring pattern. The wiring pattern is formed such that the chamfering portion is set to a filet. Thereafter, the interlayer resin insulating layer and the wiring pattern are further formed. Here, since the filet is added to the corner portion, no wiring pattern is made thin and is disconnected in the crossing portion. Further, since the filet is added to the corner portion, no stress is concentrated to the crossing portion in order that no wiring pattern be disconnected. Further, no air bubbles are left between the crossing portion of the wiring pattern and the interlayer resin insulating layer. Accordingly, reliability of the printed wiring board is improved.
To achieve the above objects, claim 6 resides in a printed wiring board having a conductor portion and a wiring pattern and technically characterized in that
a narrow width portion is formed in the wiring pattern in accordance with a distance from an adjacent conductor portion.
In the printed wiring board of claim 6, the narrow width portion is formed in the wiring pattern in accordance with a distance from an adjacent conductor portion so that the insulating distance between the wiring pattern and the conductor portion is held and density of the wiring pattern can be increased. Here, no width of the wiring pattern is narrowed in a portion capable of holding the insulating distance from the conductor portion so that possibility of disconnection is reduced and yield is increased.
Claim 7 resides in a printed wiring board having conductor portions and a wiring pattern and technically characterized in that
the width of a portion of said wiring pattern located between said conductor portions is narrowed.
In the printed wiring board of claim 7, the insulating distances between the wiring pattern and the conductor portions are held and wiring density can be increased by narrowing the width of the portion of the wiring pattern located between the conductor portions. Here, no width of the wiring pattern is narrowed in a portion capable of holding the insulating distances between the wiring pattern and the conductor portions, i.e., a portion unlocated between the conductor portions. Therefore, possibility of disconnection is reduced and yield is increased.
In the printed wiring board of claim 8, the width of the wiring pattern is narrowed on its central side when one wiring pattern is located between the conductor portions. Therefore, the insulating distances from both the conductor portions can be held.
In claim 7, claim 9 is technically characterized in that, when the said wiring patterns are located between the said conductor portions, widths of the wiring patterns are respectively narrowed on sides opposed to the conductor portions.
In the printed wiring board of claim 9, the widths of the wiring patterns are respectively narrowed on sides opposed to the conductor portions when the two wiring patterns are located between the conductor portions. Therefore, the insulating distances from both the conductor portions can be held.
In claim 7, claim 10 is technically characterized in that, when at least three said wiring patterns are located between said conductor portions,
a width of at least one portion of a central wiring pattern except for wiring patterns on both sides of the central wiring pattern is narrowed on a central side, and
widths of the wiring patterns on both the sides are respectively narrowed on sides opposed to the conductor portions.
In the printed wiring board of claim 10, when three wiring patterns or more are located between the conductor portions, the width of at least one portion of the central wiring pattern except for the wiring patterns on both the sides is narrowed on the central side, and the widths of the wiring patterns on both the sides are respectively narrowed on sides opposed to the conductor portions. Therefore, the insulating distances from both the conductor portions and the insulating distances between the wiring patterns can be held.
In the printed wiring board of claim 11, wiring pattern sides of the conductor portions are notched. Therefore, the insulating distances between the wiring patterns and both the conductor portions can be held.
In the printed wiring board of claim 12, the pitch of wiring patterns of a multilayer build-up wiring board can be narrowed. Therefore, wiring density can be increased without increasing the number of build-up layers.
In the printed wiring board of claim 13, the pitch between via hole lands or pads for mounting can be narrowed. Therefore, wiring density can be increased without increasing the number of build-up layers.
To achieve the above objects, claim 14 resides in a printed wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated with each other, and technically characterized in that
a dummy conductor is arranged around a wiring pattern constituting said conductor layer.
Claim 15 resides in a printed wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated with each other, and technically characterized in that
a dummy conductor is arranged around plural wiring patterns constituting said conductor layer.
In the invention of each of claims 14 and 15, the dummy conductor is arranged around the wiring patterns. Accordingly, when the conductor layer is formed by electrolytic plating, no concentration of an electric field is caused and the wiring patterns can be formed in predetermined thicknesses. Therefore, an isolated wiring pattern and a wiring pattern in a close portion can be formed in uniform thicknesses. Further, the thickness of the interlayer resin insulating layer in an upper layer of the wiring patterns can be uniformed. Accordingly, electric characteristics of the printed wiring board can be improved. It is carefully additionally noted that the wiring patterns and the dummy conductor in the present invention may not be formed on a so-called core substrate.
In the invention of claim 16, a width of the dummy conductor is set to one to three times a minimum width of the wiring pattern. Therefore, no concentration of an electric field is caused and the wiring pattern and the dummy conductor can be formed in predetermined thicknesses.
In the invention of claim 17, the distance between the dummy conductor and the wiring pattern is set to one to three times a minimum width of the wiring pattern. Therefore, no concentration of an electric field is caused, and the wiring pattern and the dummy conductor can be formed in predetermined thicknesses.
Claim 18 resides in a printed wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated with each other, and technically characterized in that
a dummy conductor is arranged around an isolated land constituting said conductor layer.
In the invention of claim 18, the dummy conductor is arranged around the isolated land. Therefore, when the conductor layer is formed by electrolytic plating, there is no concentration of an electric field caused and the isolated land can be formed in a predetermined thickness. Therefore, the isolated land and a land in a close portion can be formed in uniform thicknesses so that electric characteristics of the printed wiring board can be improved.
In the invention of claim 19, a peripheral portion of the isolated land is surrounded by the dummy conductor. Therefore, it is possible that from the exterior the isolated land which is influenced by noises, etc. can be reduced.
In the invention of claim 20, the width of the dummy conductor is set to ⅙ to 3 times a diameter of the land. Therefore, no concentration of an electric field is caused, and the land and the dummy conductor can be formed in predetermined thicknesses.
In the invention of claim 21, a minimum distance between the dummy conductor and the isolated land is set to ⅙ to 3 times the land diameter. Therefore, no concentration of an electric field is caused, and the land and the dummy conductor can be formed in predetermined thicknesses.
Claim 22 resides in a printed wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated with each other, and technically characterized in that
a dummy conductor is arranged in said conductor layer and a filet is formed in a crossing portion of this dummy conductor and another dummy conductor.
In the invention of claim 22, the dummy conductors can be properly connected to each other since the filet is formed in the crossing portion of the dummy conductors.
Claim 23 resides in a printed wiring board having an interlayer resin insulating layer and a conductor layer alternately laminated with each other, and technically characterized in that
a dummy conductor is arranged in said conductor layer and a filet is formed in a right angle or acute angle portion in a crossing portion of this dummy conductor and another dummy conductor.
In the invention of claim 23, the filet is formed in the right angle or acute angle portion in the crossing portion of the dummy conductors. Therefore, no right angle and acute angle portions are formed so that no crack is caused by stress concentration caused by a corner portion.
In the printed wiring board of claim 24, interlayer resin insulating layers and conductor layers are alternately laminated with each other, and build-up wiring layers are formed on both faces of a core substrate by connecting the conductor layers to each other by a via hole, and the printed wiring board is technically characterized in that
a circular land is formed in a through hole formed in said core substrate and the via hole is connected to this land.
In the printed wiring board of claim 24, the via hole is formed on the land of the through hole and no pad for connection of the via hole is added to the land so that the number of through holes arranged in the core substrate can be increased.
In the printed wiring board of claim 25, a radius of the through hole is set to be equal to or smaller than 175 xcexcm and is equal to or greater than 125 xcexcm. When the radius of the through hole exceeds 175 xcexcm, the number of through holes arranged in the core substrate is reduced. In contrast to this, when the radius of the through hole is smaller than 125 xcexcm, it is difficult to form the through hole by a drill. On the other hand, a radius of the land is greater by 75 xcexcm to 175 xcexcm than the radius of the through hole. This is because 75 xcexcm in total is obtained as a minimum value able to be technically set by adding a diameter 25 xcexcm of the via hole, an error xc2x112.5 (25 in total) xcexcm of an opening for the via hole with respect to the land, and an error 25 xcexcm of the land with respect to a passing hole. On the other hand, this is also because 175 xcexcm is obtained in total as a minimum value capable of being economically set in mass production by adding a diameter 35 xcexcm of the via hole, an error xc2x120 (40 in total) xcexcm of the opening for the via hole with respect to the land, and an error 100 xcexcm of the land with respect to the passing hole. Namely, the via hole can be arranged technically and economically on the land by forming the land such that the radius of the land is greater by 75 xcexcm to 175 xcexcm than the radius of the through hole.
A manufacturing method of a printed wiring board in claim 26 is technically characterized in that the manufacturing method comprises:
(a) a process for boring a passing hole for a through hole in a substrate for multiple chamfering by a drill;
(b) a process for forming a metallic film within said passing hole;
(c) a process for forming a land in an opening portion of said passing hole;
(d) a process for coating said substrate with resin constituting an interlayer resin insulating layer;
(e) a process for performing position alignment with said land and forming an opening having a diameter equal to or smaller than 35 xcexcm in said resin on said land; and
(f) a process for forming a metallic film in said opening and setting this opening to a via hole;
a radius of said land is set to be equal to or greater than a value obtained by adding a radius of said passing hole, an error range of the land with respect to said passing hole, the opening diameter, and an error range of the opening with respect to said land, and is also set to be equal to or smaller than 700 xcexcm.
In the invention of claim 26, the radius of the land is set to be equal to or greater than a value obtained by adding a radius of the passing hole, an error range of the land with respect to the passing hole, the opening diameter, and an error range of the opening with respect to said land. Accordingly, the via hole can be formed on the land. Here, when the land diameter is set to be equal to or smaller than 700 xcexcm, an arranging density of the through hole can be increased in comparison with a construction in which a land for arranging the via hole is added to the land of the prior art.
In the invention of claim 27, the radius of the land is set to range from 200 xcexcm to 350 xcexcm. This is because 200 xcexcm is obtained in total as a minimum value able to be technically set by adding a radius 125 xcexcm of the through hole, a diameter 25 xcexcm of the via hole, an error xc2x112.5 (25 in total) xcexcm of an opening for the via hole with respect to the land, and an error 25 xcexcm of the land with respect to a passing hole. On the other hand, 350 xcexcm is obtained in total (radius) as a minimum value able to be economically set in mass production by adding a radius 175 xcexcm of the through hole, a diameter 35 xcexcm of the via hole, an error xc2x120 (40 in total) xcexcm of the opening for the via hole, and an error 100 xcexcm of the land with respect to the passing hole. The via hole can be arranged on the land by setting the land radius to this value in a high economical range capable of being technically set.
A full additive method or a semi-additive method can be adopted in the above printed wiring board. In the full additive method, a plating resist is formed on a substrate and a metallic layer is deposited in an opening portion of this plating resist and is set to a wiring pattern. In the semi-additive method, after a metallic layer is formed on a substrate, a plating resist is formed and a metallic layer is further deposited in an opening portion of this plating resist. After the plating resist is removed, a wiring pattern is formed by removing the metallic layer below the plating resist.
In the present invention, it is desirable to use an adhesive for electroless plating as the above interlayer resin insulating layer. In this adhesive for electroless plating, it is optimal that heat resisting resin particles soluble to a hardened acid or oxidizing agent are dispersed into unhardened heat resisting resin which is difficult to be soluble to an acid or an oxidizing agent.
The heat resisting resin particles are dissolved and removed by processing these resin particles using an acid or an oxidizing agent and a coarsened face constructed by an anchor formed in the shape of an octopus trap can be formed on a layer surface.
In the above adhesive for electroless plating, the above heat resisting resin particles particularly hardened are desirably constructed by using {circle around (1)} heat resisting resin powder having an average particle diameter equal to or smaller than 10 xcexcm, {circle around (2)} cohesive particles formed by aggregating heat resisting resin powder having an average particle diameter equal to or smaller than 2 xcexcm, {circle around (3)} a mixture of heat resisting powder resin powder having an average particle diameter from 2 to 10 xcexcm and heat resisting resin powder having an average particle diameter equal to or smaller than 2 xcexcm, {circle around (4)} pseudo-particles in which at least one kind of heat resisting resin powder or inorganic powder having an average particle diameter equal to or smaller than 2 xcexcm is attached to the surface of heat resisting resin powder having an average particle diameter from 2 to 10 xcexcm, {circle around (5)} a mixture of heat resisting powder resin powder having an average particle diameter from 0.1 to 0.8 xcexcm and heat resisting resin powder having an average particle diameter greater than 0.8 xcexcm and smaller than 2 xcexcm, and {circle around (6)} heat resisting powder resin powder having an average particle diameter from 0.1 to 1.0 xcexcm. This is because these materials can form a more complicated anchor.
A depth of the coarsened face is preferably set to secure a close attaching property such that Rmax=0.01 to 20 xcexcm. In particular, Rmax preferably ranges from 0.1 to 5 xcexcm in the semi-additive method since an electroless plating film can be removed while the close attaching property is secured.
The heat resisting resin difficult to be soluble to an acid or an oxidizing agent mentioned above is desirably constructed by xe2x80x9ca resin complex constructed by thermosetting resin and thermoplastic resinxe2x80x9d, or xe2x80x9ca resin complex constructed by photosensitive resin and thermoplastic resinxe2x80x9d. The former has a high heat resisting property. The latter is desirable since the opening for the via hole can be formed by photolithography.
The above thermosetting resin can be constructed by using epoxy resin, phenol resin, polyimide resin, etc. When the thermosetting resin is photosensitized, a thermosetting group acrylic-reacts on methacrylic acid, acrylic acid, etc. Acrylate of the epoxy resin is particularly optimal.
The epoxy resin can be constructed by using epoxy resin of novolak type such as phenol novolak type, cresol novolak type, etc., dicyclopentadiene-modified alicyclic epoxy resin, etc.
The thermoplastic resin can be constructed by using polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyether imide (PI), etc.
A mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably set such that thermosetting resin (photosensitive resin)/thermoplastic resin=95/5 to 50/50. This is because a high toughness value can be secured without reducing a heating resisting property.
A mixing weight ratio of the above heat resisting resin particles is set preferably to range from 5 to 50 weight % and to desirably range from 10 to 40 weight % with respect to the solid content of a heat resisting resin matrix.
The heat resisting resin particles are preferably constructed by amino resin (melamine resin, urea resin, guanamine resin), epoxy resin, etc.
The adhesive may be constructed by two layers having different compositions.
Various kinds of resins can be used as a solder resist layer added to a surface of the multilayer build-up wiring board. For example, it is possible to use bisphenol A-type epoxy resin, acrylate of bisphenol A-type epoxy resin, novolak type epoxy resin, resin formed by hardening acrylate of novolak type epoxy resin by an amine-system hardening agent, an imidazole hardening agent, etc.
There is a case in which such a solder resist layer is separated since the solder resist layer is constructed by resin having a stiff skeleton. Therefore, the separation of the solder resist layer can be also prevented by arranging a reinforcing layer.
The above acrylate of the novolak type epoxy resin can be constructed by using epoxy resin in which glycidyl ether of phenol novolak and cresol novolak reacts with acrylic acid, methacrylic acid, etc.
The above imidazole hardening agent is desirably formed in a liquid state at 25xc2x0 C. since the imidazole hardening agent can be uniformly mixed in the liquid state.
Such a liquid state imidazole hardening agent can be constructed by using 1-benzyl-2-methylimidazole (product name: 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ).
An adding amount of this imidazole hardening agent is desirably set to range from 1 to 10 weight % with respect to a total solid content of the above solder resist composition substance. This is because the imidazole hardening agent is easily uniformed and mixed if the adding amount lies within this range.
A composition substance prior to the hardening of the above solder resist is desirably constructed by using a solvent of a glycol ether system as a solvent.
In the solder resist layer using such a composition substance, no free acid is caused and no copper pad surface is oxidized. Further, a harmful property with respect to a human body is low.
Such a solvent of the glycol ether system is constructed by using the following structural formula, it is particularly desirably using at least one kind elected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG). This is because these solvents can perfectly dissolve benzophenone and Michler""s ketone as reaction starting agents at a heating temperature from about 30 to 50xc2x0 C.
CH3Oxe2x80x94(CH2CH2O)nxe2x80x94CH3(n=1 to 5)
This solvent of the glycol ether system preferably has 10 to 70 wt % with respect to a total weight amount of the solder resist composition substance.
As explained above, various kinds of antifoaming and leveling agents, thermosetting resin for improving a heat resisting property and an antibasic property and giving a flexible property, a photosensitive monomer for improving resolution, etc. can be further added to the solder resist composition substance.
For example, the leveling agent is preferably constructed by monomer of acrylic ester. A starting agent is preferably constructed by Irugacure 1907 manufactured by CHIBAGAIGI. A photosensitizer is preferably constructed by DETX-S manufactured by NIHON KAYAKU.
Further, a coloring matter and a pigment may be added to the solder resist composition substance since a wiring pattern can be hidden. This coloring matter is desirably constructed by using phthalocyaline green.
Bisphenol type epoxy resin can be used as the above thermosetting resin as an adding component. In this bisphenol type epoxy resin, there are bisphenol A-type epoxy resin and bisphenol F-type epoxy resin. The former is preferable when an antibasic property is seriously considered. The latter is preferable when low viscosity is required (when a coating property is seriously considered).
A polyhydric acrylic-system monomer can be used as the above photosensitive monomer as an adding component since the polyhydric acrylic-system monomer can improve resolution. For example, DPE-6A manufactured by NIHON KAYAKU and R-604 manufactured by KYOEISYA KAGAKU can be used as the polyhydric acrylic-system monomer.
These solder resist composition substances preferably have 0.5 to 10 Paxc2x7s in viscosity at 25xc2x0 C. and more desirably have 1 to 10 Paxc2x7s in viscosity since these solder resist composition substances are easily coated by a roll coater in these cases.